This invention pertains to the field of microelectronics, and more particularly to the field of fabricating and interconnecting extremely small semiconductor devices, commonly referred to as xe2x80x9cchips.xe2x80x9d
The present invention is related to certain inventions assigned to the assignee of the present invention. These are disclosed in co-pending applications YOR920010249US1 and YOR920010217US1.
Increased levels of integration in the silicon transistor technology over the last two decades have facilitated the migration from large scale integrated (LSI) to very large scale integrated (VLSI) and now to ultra-large scale integrated (ULSI) circuits for use in silicon chips for computing, communication and micro controller applications. Optimum utilization of these highly integrated silicon chips requires a more space efficient packaging with supporting devices such as memory chips. Further, with the advent of mobile communication devices, hand held organizers and computing devices, there has also been a push to integrate such varied functions into a single compact system. This in turn has led to the push in the microelectronics industry towards system-on-a-chip (SOC) approach.
Simply stated, the SOC approach attempts to integrate as many of these different device functionalities on the same silicon chip so that a single large chip can provide a variety of functions to the end user. Although conceptually very attractive, such an approach is practically daunting due to several reasons. First, the materials, fabrication processes and feature sizes optimum for the different microelectronic devices (such as memory chips, logic chips, wireless communication chips, etc.) are quite different from each other. Combining them all onto the same chip implies making compromises that can limit the performance achievable in each of the device blocks in the SOC. Second, integration of a large number of functional blocks requires a large chip size with many levels of wiring constructed on the chip. Both these factors tend to reduce the yield and increase the cost per chip, which is undesirable. Third, one has to design and build every unique combination of functions (e.g., memory and microprocessor, wireless communication and microprocessor, etc.) leading to a large variety of chip part numbers and product mix that is not conducive to low cost manufacturing. Last, the expertise required for combining a diverse set of materials, process and integration schemes on a single SOC is often not available in a single enterprise as these are currently part of different microelectronic businesses.
An attractive alternative to SOC is system-on-a-package or SOP wherein a number of chips, each optimized for its unique function and perhaps manufactured in different factories specially tailored to produce the specific chips, are combined on a first level packaging carrier that interconnects them and allows the resulting package to function as a single system. The level of interconnection and input-outputxe2x80x94(I/O) density required in such a package is expected to be far greater than those currently available in printed circuit board or multilayer ceramic technologies. Since this SOP carrier with chips assembled on it is expected to replace an SOC, it is reasonable to expect that the interconnect and I/O densities should be somewhere between those used in the far back end of the line (FBEOL) interconnect levels on chips (typically wiring and vias on 500 nm to 1000 nm pitch) and the most aggressive packaging substrates (typically vias and wiring on 10,000 to 20,000 nm pitch). Extension of the FBEOL processes at the required wiring size and pitch for the SOP carrier is feasible if the carrier itself is made of silicon. In addition, however, the carrier would be required to support a high I/O density in order to interconnect the various device chips mounted on it. Greater the granularity of the system, that is, finer the division of the system into sub-units or chips, greater will be the number of I/Os required. It is expected that such I/O densities will necessitate bonding pads that are on the order of 5 to 10 xcexcm size and spaces which are presently outside the realm of possibility of typical packaging I/O pads which are at least 10 to 20 times coarser in size and spacing.
It is therefore highly desirable to enable a microjoining structure to interconnect several chips on to a system-on-a-package carrier to achieve significantly higher input/output density between the chips as compared to the current state-of-the-art.
Accordingly, a primary object of the present invention is to make possible ultra high density of interconnections facilitating the use in ultra large scale integrated circuit chips (logic, microprocessor, memory, network switching). Current flip chip solder technology can achieve only about 75 xcexcm pads on 150 xcexcm centers. Our method is capable of aerial densities up to 1000 times or more this level. This is made possible by the unique process flow that does not require any special lithographic steps in the fabrication of the contact pads and uses the fine features in these device chips at the back end of the line (BEOL) interconnection level.
A structure is proposed, comprising a fine pitch (down to about 2.5 xcexcm pads on 5 xcexcm centers) array of interconnects between a device component (semiconductor chip, optical device such as a laser, discrete or integrated passive components, and the like) also referred to as a chiplet; and a carrier that houses one or many of these components. The carrier can be a silicon, ceramic or organic substrate but most preferably made of silicon to achieve the highest interconnection density. The joining metallurgy on the device side comprises an adhesion layer, solder reaction barrier layer and a fusible solder joint ball. On the carrier side the matching contact pads are intentionally made larger than the ones on the device side and comprise an adhesion layer, solder reaction barrier layer and a noble metal protection/solder wetting layer. Alternately, the said larger contact pads can be part of the top level of the device and the fusible solder bearing structure integrated on the carrier if so desired.
The foregoing and still further objects and advantages of the present invention will be more apparent from the following detailed explanation of the preferred embodiments of the invention in connection with the accompanying drawing.